X9c104p 65r6y

X9C102, X9C103, X9C104, X9C503

®

Data Sheet

December 20, 2006

FN8222.1

DESCRIPTION

Digitally Controlled Potentiometer (XD™) FEATURES • Solid-state potentiometer • 3-wire serial interface • 100 wiper tap points —Wiper position stored in nonvolatile memory and recalled on power-up • 99 resistive elements —Temperature compensated —End to end resistance, ±20% —Terminal voltages, ±5V • Low power CMOS —VCC = 5V —Active current, 3mA max. —Standby current, 750µA max. • High reliability —Endurance, 100,000 data changes per bit — data retention, 100 years • X9C102 = 1kΩ • X9C103 = 10kΩ • X9C503 = 50kΩ • X9C104 = 100kΩ • Packages —8 Ld SOIC and 8 Ld PDIP • Pb-free plus anneal available (RoHS compliant)

The X9Cxxx are Intersil digitally controlled (XD) potentiometers. The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a three-wire interface. The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: – control – parameter adjustments – signal processing

BLOCK DIAGRAM U/D INC CS

7-Bit Up/Down Counter

VCC (Supply Voltage)

RH/VH

99 98 97

Up/Down (U/D) Increment (INC) Device Select (CS)

7-Bit Nonvolatile Memory

VH/RH Control and Memory

RW/VW VL/RL

VSS (Ground)

VCC GND

General

Store and Recall Control Circuitry

96 One of OneHundred Decoder 2

Transfer Gates

Resistor Array

1 0 RL/VL RW/VW Detailed

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a ed trademark of Intersil Americas Inc. XD is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

X9C102, X9C103, X9C104, X9C503 PIN CONFIGURATION DIP/SOIC INC

1

8

VCC

U/D

2

7

CS

VH/RH

3

6

VL/RL

VSS

4

5

VW/RW

X9C102/103/104/503

ORDERING INFORMATION PART NUMBER

PART MARKING

RTOTAL (kΩ)

TEMPERATURE RANGE (°C)

1

PACKAGE

PKG. DWG. #

X9C102P

X9C102P

0 to 70

8 Ld PDIP

MDP0031

X9C102PZ (Note)

X9C102P Z

0 to 70

8 Ld PDIP (Pb-free)

MDP0031

X9C102PI

X9C102P I

-40 to 85

8 Ld PDIP

MDP0031

X9C102PIZ (Note)

X9C102P ZI

-40 to 85

8 Ld PDIP (Pb-free)

MDP0031

X9C102S*, **

X9C102S

0 to 70

8 Ld SOIC

MDP0027

X9C102SZ* (Note)

X9C102S Z

0 to 70

8 Ld SOIC (Pb-free)

MDP0027

X9C102SI*, **

X9C102S I

-40 to 85

8 Ld SOIC

MDP0027

X9C102SIZ*, ** (Note)

X9C102S ZI

-40 to 85

8 Ld SOIC (Pb-free)

MDP0027

X9C103P

X9C103P

0 to 70

8 Ld PDIP

MDP0031

10

X9C103PZ (Note)

X9C103P Z

0 to 70

8 Ld PDIP (Pb-free)

MDP0031

X9C103PI

X9C103P I

-40 to 85

8 Ld PDIP

MDP0031

X9C103PIZ (Note)

X9C103P ZI

-40 to 85

8 Ld PDIP (Pb-free)

MDP0031

X9C103S*, **

X9C103S

0 to 70

8 Ld SOIC

MDP0027

X9C103S Z

0 to 70

8 Ld SOIC (Pb-free)

MDP0027

X9C103SI*, **

X9C103S I

-40 to 85

8 Ld SOIC

MDP0027

X9C103SIZ*, ** (Note)

X9C103S ZI

-40 to 85

8 Ld SOIC (Pb-free)

MDP0027

X9C103SZ*, **

(Note)

X9C503P

X9C503P

0 to 70

8 Ld PDIP

MDP0031

X9C503PZ (Note)

X9C503P Z

50

0 to 70

8 Ld PDIP (Pb-free)

MDP0031

X9C503PI

X9C503P I

-40 to 85

8 Ld PDIP

MDP0031

X9C503PIZ (Note)

X9C503P ZI

-40 to 85

8 Ld PDIP (Pb-free)

MDP0031

X9C503S*

X9C503S

0 to 70

8 Ld SOIC

MDP0027

X9C503SZ* (Note)

X9C503S Z

0 to 70

8 Ld SOIC (Pb-free)

MDP0027

X9C503SI*, **

X9C503S I

-40 to 85

8 Ld SOIC

MDP0027

X9C503SIZ*, ** (Note)

X9C503S ZI

-40 to 85

8 Ld SOIC (Pb-free)

MDP0027

X9C104P

X9C104P

0 to 70

8 Ld PDIP

MDP0031

X9C104PI

X9C104P I

-40 to 85

8 Ld PDIP

MDP0031

X9C104PIZ (Note)

X9C104P ZI

-40 to 85

8 Ld PDIP (Pb-free)

MDP0031

X9C104S*, **

X9C104S

0 to 70

8 Ld SOIC

MDP0027

X9C104SZ*, ** (Note)

X9C104S Z

0 to 70

8 Ld SOIC (Pb-free)

MDP0027

X9C104SI*, **

X9C104S I

-40 to 85

8 Ld SOIC

MDP0027

X9C104SIZ*, ** (Note)

X9C104S ZI

-40 to 85

8 Ld SOIC (Pb-free)

MDP0027

100

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel.

2

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 PIN DESCRIPTIONS Pin

Symbol

Brief Description

1

INC

Increment . The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input.

2

U/D

Up/Down. The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented.

3

RH/VH

4

VSS

5

VW/RW

VW/RW. VW/RW is the wiper terminal, and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40Ω.

6

RL/VL

RL/VL. The low (VL/RL) terminals of the X9C102/103/104/503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.

7

CS

CS. The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102/103/104/503 device will be placed in the low power standby mode until the device is selected once again.

8

VCC

VCC

RH/VH. The high (VH/RH) terminals of the X9C102/103/104/503 are equivalent to the fixed

terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.

VSS

3

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias .................... -65°C to +135°C Storage temperature ......................... -65°C to +150°C Voltage on CS, INC, U/D and VCC with respect to VSS .................................. -1V to +7V Voltage on VH/RH and VL/RL referenced to VSS ................................... -8V to +8V ΔV = |VH/RH - VL/RL| X9C102 ............................................................... 4V X9C103, X9C503, and X9C104 ......................... 10V Lead temperature (soldering, 10 seconds) ...... +300°C IW (10 seconds) ................................................. 8.8mA Power rating X9C102 ........................................ 16mW Power rating X9C103/104/503 .......................... 10mW

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS Temperature

Min.

Max.

Supply Voltage (VCC)

Limits

0°C

+70°C

X9C102/103/104/503

5V ±10%

-40°C

+85°C

Commercial Industrial

POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol

Parameter

Min.

Typ.

Max.

Unit

RTOTAL

End to end resistance variation

-20

+20

%

VVH/RH

VH terminal voltage

-5

+5

V

VVL/RL

VL terminal voltage

-5

+5

V

-4.4

4.4

mA

IW

Wiper current

RW

Wiper resistance

40

Noise (5) Resolution Absolute Relative

linearity(1)

linearity(2)

Ω dBV

1

%

-1 -0.2

Wiper Current = ±1mA Ref. 1kHz

+1

MI(3)

VW(n)(actual) - VW(n)(expected)

+0.2

MI(3)

VW(n + 1)(actual) - [VW(n) + MI]

RTOTAL temperature coefficient

±300(5)

ppm/°C

X9C103/503/104

RTOTAL temperature coefficient

±600(5)

ppm/°C

X9C102

±20

ppm/°C

10/10/25

pF

Ratiometric temperature coefficient CH/CL/CW

100

-120

Test Conditions/Notes

Potentiometer capacitances

See Circuit #3, Macro Model

(5)

Notes: (1) (2) (3) (4) (5)

Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI. 1 MI = Minimum Increment = RTOT/99 Typical values are for TA = +25°C and nominal supply voltage. This parameter is not 100% tested.

4

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol

Min. Typ.(4)

Parameter

ICC

VCC active current

ISB

Standby supply current

ILI

CS, INC, U/D input leakage current

VIH

CS, INC, U/D input HIGH voltage

VIL

CS, INC, U/D input LOW voltage

CIN(5)

Max.

Unit

1

3

mA

CS = VIL, U/D = VIL or VIH and INC = 0.4V to 2.4V @ max. tCYC

200

750

µA

CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V

±10

µA

VIN = VSS to VCC

2

V 0.8

CS, INC, U/D input capacitance

Test Conditions

10

V pF

VCC = 5V, VIN = VSS, TA = 25°C, f = 1MHz

ENDURANCE AND DATA RETENTION Parameter

Min.

Unit

Minimum endurance

100,000

Data changes per bit per

Data retention

100

years

Test Circuit #1

Test Circuit #2

Test Circuit #3 Macro Model

VH/RH

V R /R H

Test Point VS

Test Point V W /R W V L /R L

VW/RW Force Current VL/RL

RTOTAL

RL CL 10pF

RH

CH CW

10pF

25pF RW

A.C. CONDITIONS OF TEST Input pulse levels

0V to 3V

Input rise and fall times

10ns

Input reference levels

1.5V

5

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 A.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Limits Symbol tCl tlD tDI tlL tlH tlC tH tH tIW (5) tCYC tR, tF(5) tPU(5) tR VCC(5)

Parameter CS to INC setup INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period INC inactive to CS inactive CS deselect time (STORE) CS deselect time (NO STORE) INC to VW/RW change INC cycle time INC input rise and fall time Power-up to wiper stable VCC power-up rate

Typ.(6)

Min. 100 100 2.9 1 1 1 20 100

Max.

Unit ns ns µs µs µs µs ms ns µs µs µs µs V/ms

100 2 500 500 0.2

50

POWER-UP AND DOWN REQUIREMENTS At all times, voltages on the potentiometer pins must be less than ±VCC. The recall of the wiper position from nonvolatile memory is not in effect until the VCC supply reaches its final value. The VCC ramp rate spec is always in effect. A.C. TIMING CS tCYC tCI

tIL

tIC

tIH

tH 90% 90% 10%

INC tID

tDI

tF

tR

U/D tIW MI

VW

(8)

Notes: (6) Typical values are for TA = 25°C and nominal supply voltage. (7) This parameter is periodically sampled and not 100% tested. (8) MI in the A.C. timing diagram refers to the minimum incremental change in the VW output due to a change in the wiper position.

6

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 PIN NAMES

DETAILED PIN DESCRIPTIONS

Symbol

RH/VH and RL/VL The high (VH/RH) and low (VL/RL) terminals of the X9C102/103/104/503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW/VW VW/RW is the wiper terminal, and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40Ω. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102/103/104/503 device will be placed in the low power standby mode until the device is selected once again. PIN CONFIGURATION DIP/SOIC INC

1

8

VCC

U/D

2

7

CS

VH/RH

3

6

VL/RL

VSS

4

5

VW/RW

X9C102/103/104/503

7

Description

VH /RH

High Terminal

VW/RW

Wiper Terminal

VL/RL

Low Terminal

VSS

Ground

VCC

Supply Voltage

U/D

Up/Down Control Input

INC

Increment Control Input

CS

Chip Select Control Input

NC

No Connection

PRINCIPLES OF OPERATION There are three sections of the X9Cxxx: the input control, counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions the contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW/RW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored.

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 INSTRUCTIONS AND PROGRAMMING The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven-bit counter. The output of this counter is decoded to select one of one-hundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9Cxxx, move the wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on preference: system parameter changes due to temperature drift, etc...

MODE SELECTION CS

INC

U/D

Mode

L

H

Wiper Up

L

L

Wiper Down

H

X

Store Wiper Position

X

X

Standby Current

L

X

No Store, Return to Standby

L

H

Wiper Up (not recommended)

L

L

Wiper Down (not recommended)

H

SYMBOL TABLE WAVEFORM

INPUTS

OUTPUTS

Must be steady

Will be steady

May change from Low to High

Will change from Low to High

May change from High to Low

Will change from High to Low

Don’t Care: Changes Allowed

Changing: State Not Known

N/A

Center Line is High Impedance

The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained.

8

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 PERFORMANCE CHARACTERISTICS the factory for more information. APPLICATIONS INFORMATION Electronic digitally controlled (XCDP) potentiometers provide three powerful application advantages; (1) the variability and reliability of a solid-state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers VR

VR VH/RH

VW/RW

VL/RL I Three terminal potentiometer; variable voltage divider

Two terminal variable resistor; variable current

Basic Circuits Buffered Reference Voltage R1

+V

+V

Noninverting Amplifier

Cascading Techniques

+5V

+V

VS

+5V VW

VREF

VOUT

–

-5V

X

VW/RW

R2

+V

-5V

R1 VW/RW

VOUT = VW/RW (a)

Voltage Regulator

(b)

VO = (1+R2/R1)VS

Offset Voltage Adjustment R1

VIN

VO (REG)

317

R2

VS

LT311A

100kΩ –

10kΩ 10kΩ +12V

10kΩ -12V

R1

}

TL072 R2

VO

VO

}

Iadj

– +

+

9

Comparator with Hysteresis

VS

R1

VO (REG) = 1.25V (1+R2/R1)+Iadj R2

VO

–

OP-07

+

LM308A

+

R2

VUL = {R1/(R1 + R2)} VO(max) VLL = {R1/(R1 + R2)} VO(min) (for additional circuits see AN115)

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 Small Outline Package Family (SO) A D

h X 45° (N/2)+1

N

A PIN #1 I.D. MARK

E1

E

c SEE DETAIL “X”

1

(N/2)

B L1 0.010 M C A B e

H

C

A2 GAUGE PLANE

SEATING PLANE A1 0.004 C

0.010 M C A B

L

b

0.010

4° ±4°

DETAIL X

MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL

SO-8

SO-14

SO16 (0.150”)

SO16 (0.300”) (SOL-16)

SO20 (SOL-20)

SO24 (SOL-24)

SO28 (SOL-28)

TOLERANCE

NOTES

A

0.068

0.068

0.068

0.104

0.104

0.104

0.104

MAX

-

A1

0.006

0.006

0.006

0.007

0.007

0.007

0.007

±0.003

-

A2

0.057

0.057

0.057

0.092

0.092

0.092

0.092

±0.002

-

b

0.017

0.017

0.017

0.017

0.017

0.017

0.017

±0.003

-

c

0.009

0.009

0.009

0.011

0.011

0.011

0.011

±0.001

-

D

0.193

0.341

0.390

0.406

0.504

0.606

0.704

±0.004

1, 3

E

0.236

0.236

0.236

0.406

0.406

0.406

0.406

±0.008

-

E1

0.154

0.154

0.154

0.295

0.295

0.295

0.295

±0.004

2, 3

e

0.050

0.050

0.050

0.050

0.050

0.050

0.050

Basic

-

L

0.025

0.025

0.025

0.030

0.030

0.030

0.030

±0.009

-

L1

0.041

0.041

0.041

0.056

0.056

0.056

0.056

Basic

-

h

0.013

0.013

0.013

0.020

0.020

0.020

0.020

Reference

-

16

20

24

28

Reference

N

8

14

16

Rev. L 2/01

NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994

10

FN8222.1 December 20, 2006

X9C102, X9C103, X9C104, X9C503 Plastic Dual-In-Line Packages (PDIP) E

D

A2

SEATING PLANE L

N

A

PIN #1 INDEX

E1 c

e

b

A1 NOTE 5

1

eA eB

2

N/2 b2

MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL

PDIP8

PDIP14

PDIP16

PDIP18

PDIP20

TOLERANCE

A

0.210

0.210

0.210

0.210

0.210

MAX

A1

0.015

0.015

0.015

0.015

0.015

MIN

A2

0.130

0.130

0.130

0.130

0.130

±0.005

b

0.018

0.018

0.018

0.018

0.018

±0.002

b2

0.060

0.060

0.060

0.060

0.060

+0.010/-0.015

c

0.010

0.010

0.010

0.010

0.010

+0.004/-0.002

D

0.375

0.750

0.750

0.890

1.020

±0.010

E

0.310

0.310

0.310

0.310

0.310

+0.015/-0.010

E1

0.250

0.250

0.250

0.250

0.250

±0.005

e

0.100

0.100

0.100

0.100

0.100

Basic

eA

0.300

0.300

0.300

0.300

0.300

Basic

eB

0.345

0.345

0.345

0.345

0.345

±0.025

L

0.125

0.125

0.125

0.125

0.125

±0.010

N

8

14

16

18

20

Reference

NOTES

1 2

Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com 11

FN8222.1 December 20, 2006