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TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
TLE4275-Q1 5-V Low-Dropout Voltage Regulator 1 Features • • • • • • • • 1
The input capacitor, CIN, compensates for line fluctuation. Using a resistor of approximately 1 Ω in series with CIN dampens the oscillation of input inductance and input capacitance. The output capacitor, COUT, stabilizes the regulation circuit. The specification for stability is at COUT ≥ 22 μF and ESR ≤ 5 Ω, within the operating temperature range. Stability for electrolytic capacitors specifically is at COUT ≥ 68 µF within the operating temperature range. See the application report on low-temperature stability, SLVA501, for further details.
Qualified for Automotive Applications Output Voltage 5 V ± 2% Very Low Current Consumption Power-On and Undervoltage Reset Reset Low-Level Output Voltage < 1 V Very Low Dropout Voltage Short-Circuit Proof Reverse-Polarity Proof
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor through a buffer. Saturation control as a function of the load current prevents any oversaturation of the power element. The device also incorporates a number of internal circuits for protection against: overload, overtemperature, and reverse polarity.
2 Applications • • • •
Qualified for Automotive Applications Cluster Body Control Modules Heating Ventilation and Air Conditioning (HVAC)
3 Description
Device Information(1)
The TLE4275-Q1 is a monolithic integrated lowdropout voltage regulator offered in a 5-pin TO package. The device regulates an input voltage up to 45 V to VOUT = 5 V (typical). The device can drive loads up to 450 mA and is short-circuit proof. At overtemperature, the incorporated temperature protection turns off the TLE4275-Q1. The device generates a reset signal for an output voltage, VOUT,rt, of 4.65 V (typical). By the use of an external delay capacitor, one can program the reset delay time.
PART NUMBER TLE4275-Q1
PACKAGE
BODY SIZE (NOM)
DDPAK/TO-263 (5)
10.16 mm × 8.42 mm
TO-252 (5)
6.10 mm × 6.60 mm
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
4 Typical Application TLE4275 Vbat
Vout OUT
IN C1
C3
RESET
DELAY
C2
R1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
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Table of Contents 1 2 3 4 5 6 7
8 9
Features .................................................................. Applications ........................................................... Description ............................................................. Typical Application ................................................ Revision History..................................................... Pin Configuration and Functions ......................... Specifications.........................................................
1 1 1 1 2 3 4
7.1 7.2 7.3 7.4 7.5 7.6 7.7
4 4 4 4 5 5 7
Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics ..............................................
Parameter Measurement Information ................ 10 Detailed Description ............................................ 11 9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11 9.3 Feature Description................................................. 12 9.4 Device Functional Modes........................................ 12
10 Application and Implementation........................ 13 10.1 Application Information.......................................... 13 10.2 Typical Application ............................................... 13
11 Power Supply Recommendations ..................... 15 12 Layout................................................................... 15 12.1 Layout Guidelines ................................................. 15 12.2 Layout Example .................................................... 15
13 Device and Documentation ................. 16 13.1 13.2 13.3 13.4
Documentation ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................
16 16 16 16
14 Mechanical, Packaging, and Orderable Information ........................................................... 16
5 Revision History Changes from Revision H (March 2013) to Revision I
Page
•
Added Applications, Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1
•
Changed KTT values in Thermal Information table ............................................................................................................... 4
Changes from Revision G (January 2013) to Revision H •
Deleted row for θJA from Absolute Maximum Ratings table ................................................................................................... 4
Changes from Revision F (May 2011) to Revision G •
2
Page
Page
Updated Pin Functions table with PWP package pin information. ......................................................................................... 3
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6 Pin Configuration and Functions Pin Functions
KTT Package 5-Pin DDPAK/TO-263 Top View
GND
5 4 3 2 1
PIN NO. TY NA PE KT KV PW ME T U P
OUT DELAY GND RESET IN
KVU Package 5-Pin TO-252 Top View
GND
5 4 3 2 1
OUT DELAY GND RESET IN
PWP Package 20-Pin HTSSOP With Exposed Thermal Pad Top View RESET
1
20
NC
NC
2
19
IN
DELAY
3
18
NC
OUT
4
17
NC
NC
5
16
NC
NC
6
15
NC
NC
7
14
NC
GND
8
13
NC
NC
9
12
NC
NC
10
11
NC
Thermal Pad
DESCRIPTION
DEL AY
4
4
3
O
Reset delay. Connect to ground with a capacitor to set delay time.
GN D
3
3
8
O
Ground. Internally connected to heatsink
IN
1
1
19
I
Input. Connect to ground as close to device as possible, through a ceramic capacitor.
2, 5–7, 9–1 — Not connected 8, 20
NC
—
—
OU T
5
5
4
O
Output. Connect to ground with ≥ 22µF capacitor, ESR < 5 Ω at 10 kHz.
RE SET
2
2
1
I
Reset output. Open-collector output
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7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN
MAX
IN
–42
45
DELAY
–0.3
7
–1
16
–0.3
25
UNIT
VI
Input voltage range (2)
VO
Output voltage range
II
Input current
DELAY
±2
mA
IO
Output current
RESET
±5
mA
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1) (2)
OUT RESET
V V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal.
7.2 ESD Ratings VALUE V(ESD) (1) (2)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
6000
Machine model (MM) (2)
400
UNIT V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. MM ESD rating tested per JESD22-A115.
7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN
MAX
VI
Input voltage
5.5
42
UNIT V
TJ
Junction temperature
–40
150
°C
7.4 Thermal Information TLE4275-Q1 THERMAL METRIC (1)
KTT
KVU
PWP
5 PINS
5 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
32.8
40.3
39.3
RθJC(top)
Junction-to-case (top) thermal resistance
38.0
31.8
22.7
RθJB
Junction-to-board thermal resistance
5.3
17.2
19.1
ψJT
Junction-to-top characterization parameter
6.3
2.8
0.6
ψJB
Junction-to-board characterization parameter
5.4
17.1
18.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
0.7
1.5
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953) .
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7.5 Electrical Characteristics over recommended operating free-air temperature range, VI = 13.5 V, TJ = −40°C to 150°C (unless otherwise noted) (see Figure 18) PARAMETER VO
Output voltage
IO
Output current limit
MIN
TYP
MAX
IO = 5 mA to 400 mA, VI = 6 V to 28 V
TEST CONDITIONS
4.9
5
5.1
IO = 5 mA to 200 mA, VI = 6 V to 40 V
4.9
5
5.1
450
700
950
150
200
TJ ≤ 85°C
150
220
IO = 250 mA
5
10
IO = 400 mA
12
22
250
500
mV
15
30
mV
5
15
mV
Dropout voltage (1)
IO = 300 mA, Vdo = VI − VO
Load regulation
IO = 5 mA to 400 mA
Line regulation
ΔVI = 8 V to 32 V, IO = 5 mA
PSRR
Power-supply ripple rejection
fr = 100 Hz, Vr = 0.5 Vpp
DVO DT
Temperature output-voltage drift
VO,rt
RESET switching threshold
VROL
RESET output low voltage
Rext ≥ 5 kΩ, VO > 1 V
IROH
RESET output leakage current
VROH = 5 V
ID,c
RESET charging current
VD = 1 V
VDU VDRL
VDO
(1)
V
TJ = 25°C
IO = 1 mA Current consumption, Iq = II − IO
Iq
UNIT
–15
4.5
mA μA mA
60
dB
0.5
mV/K
4.65
4.8
V
0.2
0.4
V
0
10
μA
3
5.5
9
μA
RESET upper timing threshold
1.5
1.8
2.2
V
RESET lower timing threshold
0.2
0.4
0.7
V
TYP
MAX
16
22
ms
0.5
2
µs
Measured when the output voltage VO has dropped 100 mV from the nominal value obtained at VI = 13.5 V
7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER
TEST CONDITIONS
trd
RESET delay time
CD = 47 nF
trr
RESET reaction time
CD = 47 nF
MIN 10
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UNIT
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VI
t < trr
VO
VQ,rt
d∆V = ID,c d∆T CD
VD
t VDU VDRL
trr
trd
t
VRO
t Power-On Reset
Thermal Shutdown
Voltage Dip at Input
Undervoltage
Secondary Overload Spike at Output
Figure 1. Reset Timing Diagram
6
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7.7 Typical Characteristics
5.3
5.3
5.2
5.2
5.1
5.1
Output Voltage (V)
Output Voltage (V)
At TA = 25ºC
5 4.9 4.8 4.7
5 4.9 4.8 4.7
4.6 -45
-5 35 75 115 Junction Temperature (qC)
4.6 -45
155
-5 35 75 115 Junction Temperature (qC)
D011
VI = 6 V
1200
11
1100
10
1000
9
900
Output Current (mA)
Output Voltage (V)
Figure 3. Output Voltage vs Junction Temperature
12
8 7 6 5 4 3
800 700 600 500 400 300
2
200
1
100
0 1
2
3 4 5 6 7 Input Voltage (V)
8
9
0 -45
10
-5 35 75 115 Junction Temperature (qC)
D013
Figure 4. Output Voltage vs Input Voltage
155 D002
Figure 5. Output Current vs Junction Temperature
3.5
12 11
Current Consumption (mA)
3 Iq – Current Consumption (mA)
D012
VI = 28 V
Figure 2. Output Voltage vs Junction Temperature
0
155
2.5 2 1.5 1 0.5
10 9 8 7 6 5 4 3 2 1
0 0
25
50
75
100
125
150
175
200
0 0
Output Current (mA)
VI = 13.5 V
50
100 150 200 250 300 350 400 Output Current (mA) D003
VI = 13.5 V
Figure 6. Current Consumption vs Output Current
Figure 7. Current Consumption vs Output Current
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Typical Characteristics (continued) 800
8
700
7
600
6
Charge Current (PA)
Dropout Voltage (mV)
At TA = 25ºC
500 400 300 200
0
100
200 300 400 Output Current (mA)
500
2
-5 35 75 115 Junction Temperature (qC)
D009
TJ = 25°C
VI = 13.5 V
Figure 8. Dropout Voltage (Vdo) vs Output Current
155 D001
VD = 1 V
Figure 9. Charge Current (ID,C) vs Junction Temperature 100
4 VDU VDRL
3.5
90 80
3
Ripple Rejection (dB)
Delay Switching Threshold (V)
3
0 -45
0
2.5 2 1.5 1
70 60 50 40 30 20
0.5 0 -45
10 -5 35 75 115 Junction Temperature (qC)
0 10 20 50 100
155 D009
VI = 13.5 V
VI = 13.5 V
Figure 10. Delay Switching Threshold vs Junction Temperature 100
100
90
90
80
80
70 60 50 40 30
50 40 30 20 10
VI = 13.5 V
Load = 200 mA
100000
0 10
100
D005
COUT = 22 µF
Figure 12. Power-Supply Ripple Rejection vs Frequency
D004
COUT = 22 µF
60
10 1000 10000 Frequency (Hz)
Load = 1 mA
100000
70
20
0 10 20 50 100
1000 10000 Frequency (Hz)
Figure 11. Power-Supply Ripple Rejection vs Frequency
Ripple Rejection (dB)
Ripple Rejection (dB)
4
1
100
8
5
VI = 13.5 V
1000 10000 Frequency (Hz)
Load = 400 mA
100000 D006
COUT = 22 µF
Figure 13. Power-Supply Ripple Rejection vs Frequency
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Typical Characteristics (continued) At TA = 25ºC 90
Junction-to-Ambient Thermal Resistance (qC/W) on 736 mm 2
80 Junction-to-Ambient Thermal Resistance (qC/W)
100 50
1-oz Copper 2-oz Copper
70 60 50 40 30
200
400 600 800 1000 1200 Copper Land-Pad Area (mm2)
1400
2 1 0.5
50% Duty Cycle 20% Duty Cycle 10% Duty Cycle 5% Duty Cycle 2% Duty Cycle 1% Duty Cycle 0.5% Duty Cycle 0.2% Duty Cycle Non-Normalized Response
0.2 0.1 0.05
0.02 0.01 1x10-6 1x10-5 1x10-4 1x10-3 1x10-2 1x10-1 1x100 1x101 1x102 1x103 Pulse-Width Time (s) D008
20 0
20 10 5
1600 D007
Figure 14. Thermal Resistance vs Copper Land Pad Area (JEDEC 51-3 Low-K Board)
Figure 15. Thermal Resistance vs Pulse Width Time for Various Duty Cycles
Stable Region
ESR (Ω)
ESR (Ω)
Unstable Region
Stable Region
Unstable Region
Load Capacitance (µF)
Load Capacitance (µF)
Figure 16. ESR Stability vs Load Current
Figure 17. ESR Stability vs Load Capacitance
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8 Parameter Measurement Information II
IN CI2 100 nF
CI1 1000 µF
1
5
IO
OUT
COUT 22 µF Rext 5 kΩ IRO
DELAY VI ID,d
ID,c
4
2
3
RESET
GND IGND
VD
VO
VRO
CD 47 nF
Figure 18. Test Circuit
10
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9 Detailed Description 9.1 Overview The TLE4275-Q1 device is a monolithic integrated low-dropout voltage regulator offered in a 5-pin TO package. The device regulates an input voltage up to 45 V to VOUT = 5 V (typical). The device can drive loads up to 450 mA and is short circuit proof. At over temperature, the incorporated temperature protection turns off the TLE4275-Q1 device. The device generates a reset signal for an output voltage, VOUT,rt, of 4.65 V (typical). By the use of an external delay capacitor, one can program the reset delay time.
9.2 Functional Block Diagram
Temperature Sensor
Saturation Control and Protection Circuit
1
5
IN
OUT
Bandgap Reference
4
Reset Generator
DELAY
2
RESET
3 GND
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9.3 Feature Description 9.3.1 Regulated Output (OUT) The OUT terminal is the regulated 5-V output. The output has current limitation. During initial power up, the regulator has a soft start incorporated to control the initial current through the element. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. 9.3.2 Power-On-Reset (RESET) The power-on-reset is an output with an external pull up resistor to the regulated supply. The reset output remains low until the regulated VO exceeds approximately 4.65 V and the power-on-reset delay has expired. 9.3.3 Reset Delay Timer (DELAY) An external capacitor on this terminal sets the timer delay before the reset terminal is asserted high. The constant output current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. The reset pulse delay time td, is defined with the charge time of an external capacitor DELAY. Cdelay ´ VDU td = I D,c (1)
9.4 Device Functional Modes 9.4.1 Low-Voltage Tracking At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage based on the load current (IO) and switch resistance (R(SW)). This allows for a smaller input capacitor and can possibly eliminate the need of using a boost convertor during cold-crank conditions.
12
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SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information Figure 19 shows typical application circuits for the TLE4275-Q1. Based on the end-application, different values of external components can be used. An application can require a larger output capacitor during fast load steps in order to prevent a reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response.
10.2 Typical Application TLE4275 Vbat
Vout OUT
IN C1
C3
RESET
DELAY
C2
R1
GND
Figure 19. Typical Application Diagram 10.2.1 Design Requirements For this design example, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
4 to 40 V
Output voltage
5V
Output current rating
400 mA
Output capacitor range
10 to 500 µF
Output capacitor ESR range
1 mΩ to 20 Ω
DELAY capacitor range
100 pF to 500 nF
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10.2.2 Detailed Design Procedure To • • • • •
begin the design process, determine the following: Input voltage range Output voltage Output current rating Output capacitor Power-up reset delay time
10.2.2.1 Power-Up Reset Capacitance To calculate the power-up reset capacitance, use Equation 2. Cdelay ´ VDU td = I D,c
Cdelay t d =
t d ´ I D,c VDU
=
t d ´ 5.5 ´ 10-6 1.8
(2)
10.2.2.2 Thermal Consideration Calculate the power dissipated by the device according to Equation 3. PT = IO × (VI – VO) + VI × IQ
where • • • •
PT = Total power dissipation of the device. IO = output current VI = input voltage VO = output voltage
(3)
After determining the power dissipated by the device, calculate the junction temperature from the ambient temperature and the device thermal impedance. TJ = TA + RθJA × PT
(4)
10.2.3 Application Curves Load = 200 mA, Cin = 22 µF, Cout = 10 µF
CH1：Vout, CH2: Vin, CH3: Vreset. Figure 20. Power Up Waveform
14
CH1：Vout, CH2: Vin, CH3: Vreset. Figure 21. Power Down Waveform
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11 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 4 V and 40 V. This input supply must be well regulated. If the input supply is located more than a few inches from the TLE4275-Q1 device, an electrolytic capacitor with a value of 47 µF and a ceramic by capacitor are recommended to add at the input.
12 Layout 12.1 Layout Guidelines •
•
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because of the negative impact on system performance. Vias and long traces can also cause instability. Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close to the device as possible and on the same side of the PCB as the regulator.
12.2 Layout Example 180
RESET
NC
NC
IN
DELAY
NC
OUT
NC
NC
NC
NC
NC
NC
NC
GND
NC
Connect through bottom layer
Vin
Power Ground
Output filter capacitor, place close to chip Vout
Input by capacitor
Power Ground
NC
NC
NC
NC
Figure 22. TLE4275-Q1 HTSSOP Layout Design Example
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13 Device and Documentation 13.1 Documentation 13.1.1 Related Documentation For related documentation see the following: TLE4275-Q1 Low Temperature Stability, SLVA501
13.2 Trademarks All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains , acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Oct-2014
PACKAGING INFORMATION Orderable Device
Status (1)
Package Type Package Pins Package Drawing Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking (4/5)
TLE4275QKTTRQ1
ACTIVE
DDPAK/ TO-263
KTT
5
500
Green (RoHS & no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
TLE4275Q
TLE4275QKVURQ1
ACTIVE
TO-252
KVU
5
2500
Green (RoHS & no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
TLE4275Q
TLE4275QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLE4275Q
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)
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MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
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(5)
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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4-Oct-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com
4-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLE4275QKTTRQ1
Package Package Pins Type Drawing
SPQ
DDPAK/ TO-263
5
500
330.0
24.4
KTT
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm)
B0 (mm)
K0 (mm)
P1 (mm)
W Pin1 (mm) Quadrant
10.6
15.8
4.9
16.0
24.0
Q2
TLE4275QKVURQ1
TO-252
KVU
5
2500
330.0
16.4
6.9
10.5
2.7
8.0
16.0
Q2
TLE4275QPWPRQ1
HTSSOP
PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com
4-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLE4275QKTTRQ1
DDPAK/TO-263
KTT
5
500
340.0
340.0
38.0
TLE4275QKVURQ1
TO-252
KVU
5
2500
340.0
340.0
38.0
TLE4275QPWPRQ1
HTSSOP
PWP
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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Technical Documents
TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
TLE4275-Q1 5-V Low-Dropout Voltage Regulator 1 Features • • • • • • • • 1
The input capacitor, CIN, compensates for line fluctuation. Using a resistor of approximately 1 Ω in series with CIN dampens the oscillation of input inductance and input capacitance. The output capacitor, COUT, stabilizes the regulation circuit. The specification for stability is at COUT ≥ 22 μF and ESR ≤ 5 Ω, within the operating temperature range. Stability for electrolytic capacitors specifically is at COUT ≥ 68 µF within the operating temperature range. See the application report on low-temperature stability, SLVA501, for further details.
Qualified for Automotive Applications Output Voltage 5 V ± 2% Very Low Current Consumption Power-On and Undervoltage Reset Reset Low-Level Output Voltage < 1 V Very Low Dropout Voltage Short-Circuit Proof Reverse-Polarity Proof
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor through a buffer. Saturation control as a function of the load current prevents any oversaturation of the power element. The device also incorporates a number of internal circuits for protection against: overload, overtemperature, and reverse polarity.
2 Applications • • • •
Qualified for Automotive Applications Cluster Body Control Modules Heating Ventilation and Air Conditioning (HVAC)
3 Description
Device Information(1)
The TLE4275-Q1 is a monolithic integrated lowdropout voltage regulator offered in a 5-pin TO package. The device regulates an input voltage up to 45 V to VOUT = 5 V (typical). The device can drive loads up to 450 mA and is short-circuit proof. At overtemperature, the incorporated temperature protection turns off the TLE4275-Q1. The device generates a reset signal for an output voltage, VOUT,rt, of 4.65 V (typical). By the use of an external delay capacitor, one can program the reset delay time.
PART NUMBER TLE4275-Q1
PACKAGE
BODY SIZE (NOM)
DDPAK/TO-263 (5)
10.16 mm × 8.42 mm
TO-252 (5)
6.10 mm × 6.60 mm
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
4 Typical Application TLE4275 Vbat
Vout OUT
IN C1
C3
RESET
DELAY
C2
R1
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
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Table of Contents 1 2 3 4 5 6 7
8 9
Features .................................................................. Applications ........................................................... Description ............................................................. Typical Application ................................................ Revision History..................................................... Pin Configuration and Functions ......................... Specifications.........................................................
1 1 1 1 2 3 4
7.1 7.2 7.3 7.4 7.5 7.6 7.7
4 4 4 4 5 5 7
Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics ..............................................
Parameter Measurement Information ................ 10 Detailed Description ............................................ 11 9.1 Overview ................................................................. 11
9.2 Functional Block Diagram ....................................... 11 9.3 Feature Description................................................. 12 9.4 Device Functional Modes........................................ 12
10 Application and Implementation........................ 13 10.1 Application Information.......................................... 13 10.2 Typical Application ............................................... 13
11 Power Supply Recommendations ..................... 15 12 Layout................................................................... 15 12.1 Layout Guidelines ................................................. 15 12.2 Layout Example .................................................... 15
13 Device and Documentation ................. 16 13.1 13.2 13.3 13.4
Documentation ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................
16 16 16 16
14 Mechanical, Packaging, and Orderable Information ........................................................... 16
5 Revision History Changes from Revision H (March 2013) to Revision I
Page
•
Added Applications, Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation section, and Mechanical, Packaging, and Orderable Information section ................................................................................................................................................................................... 1
•
Changed KTT values in Thermal Information table ............................................................................................................... 4
Changes from Revision G (January 2013) to Revision H •
Deleted row for θJA from Absolute Maximum Ratings table ................................................................................................... 4
Changes from Revision F (May 2011) to Revision G •
2
Page
Page
Updated Pin Functions table with PWP package pin information. ......................................................................................... 3
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SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
6 Pin Configuration and Functions Pin Functions
KTT Package 5-Pin DDPAK/TO-263 Top View
GND
5 4 3 2 1
PIN NO. TY NA PE KT KV PW ME T U P
OUT DELAY GND RESET IN
KVU Package 5-Pin TO-252 Top View
GND
5 4 3 2 1
OUT DELAY GND RESET IN
PWP Package 20-Pin HTSSOP With Exposed Thermal Pad Top View RESET
1
20
NC
NC
2
19
IN
DELAY
3
18
NC
OUT
4
17
NC
NC
5
16
NC
NC
6
15
NC
NC
7
14
NC
GND
8
13
NC
NC
9
12
NC
NC
10
11
NC
Thermal Pad
DESCRIPTION
DEL AY
4
4
3
O
Reset delay. Connect to ground with a capacitor to set delay time.
GN D
3
3
8
O
Ground. Internally connected to heatsink
IN
1
1
19
I
Input. Connect to ground as close to device as possible, through a ceramic capacitor.
2, 5–7, 9–1 — Not connected 8, 20
NC
—
—
OU T
5
5
4
O
Output. Connect to ground with ≥ 22µF capacitor, ESR < 5 Ω at 10 kHz.
RE SET
2
2
1
I
Reset output. Open-collector output
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7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN
MAX
IN
–42
45
DELAY
–0.3
7
–1
16
–0.3
25
UNIT
VI
Input voltage range (2)
VO
Output voltage range
II
Input current
DELAY
±2
mA
IO
Output current
RESET
±5
mA
TJ
Operating junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1) (2)
OUT RESET
V V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal.
7.2 ESD Ratings VALUE V(ESD) (1) (2)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
6000
Machine model (MM) (2)
400
UNIT V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. MM ESD rating tested per JESD22-A115.
7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN
MAX
VI
Input voltage
5.5
42
UNIT V
TJ
Junction temperature
–40
150
°C
7.4 Thermal Information TLE4275-Q1 THERMAL METRIC (1)
KTT
KVU
PWP
5 PINS
5 PINS
20 PINS
RθJA
Junction-to-ambient thermal resistance
32.8
40.3
39.3
RθJC(top)
Junction-to-case (top) thermal resistance
38.0
31.8
22.7
RθJB
Junction-to-board thermal resistance
5.3
17.2
19.1
ψJT
Junction-to-top characterization parameter
6.3
2.8
0.6
ψJB
Junction-to-board characterization parameter
5.4
17.1
18.9
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
0.7
1.5
(1)
4
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953) .
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7.5 Electrical Characteristics over recommended operating free-air temperature range, VI = 13.5 V, TJ = −40°C to 150°C (unless otherwise noted) (see Figure 18) PARAMETER VO
Output voltage
IO
Output current limit
MIN
TYP
MAX
IO = 5 mA to 400 mA, VI = 6 V to 28 V
TEST CONDITIONS
4.9
5
5.1
IO = 5 mA to 200 mA, VI = 6 V to 40 V
4.9
5
5.1
450
700
950
150
200
TJ ≤ 85°C
150
220
IO = 250 mA
5
10
IO = 400 mA
12
22
250
500
mV
15
30
mV
5
15
mV
Dropout voltage (1)
IO = 300 mA, Vdo = VI − VO
Load regulation
IO = 5 mA to 400 mA
Line regulation
ΔVI = 8 V to 32 V, IO = 5 mA
PSRR
Power-supply ripple rejection
fr = 100 Hz, Vr = 0.5 Vpp
DVO DT
Temperature output-voltage drift
VO,rt
RESET switching threshold
VROL
RESET output low voltage
Rext ≥ 5 kΩ, VO > 1 V
IROH
RESET output leakage current
VROH = 5 V
ID,c
RESET charging current
VD = 1 V
VDU VDRL
VDO
(1)
V
TJ = 25°C
IO = 1 mA Current consumption, Iq = II − IO
Iq
UNIT
–15
4.5
mA μA mA
60
dB
0.5
mV/K
4.65
4.8
V
0.2
0.4
V
0
10
μA
3
5.5
9
μA
RESET upper timing threshold
1.5
1.8
2.2
V
RESET lower timing threshold
0.2
0.4
0.7
V
TYP
MAX
16
22
ms
0.5
2
µs
Measured when the output voltage VO has dropped 100 mV from the nominal value obtained at VI = 13.5 V
7.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER
TEST CONDITIONS
trd
RESET delay time
CD = 47 nF
trr
RESET reaction time
CD = 47 nF
MIN 10
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UNIT
5
TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
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VI
t < trr
VO
VQ,rt
d∆V = ID,c d∆T CD
VD
t VDU VDRL
trr
trd
t
VRO
t Power-On Reset
Thermal Shutdown
Voltage Dip at Input
Undervoltage
Secondary Overload Spike at Output
Figure 1. Reset Timing Diagram
6
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7.7 Typical Characteristics
5.3
5.3
5.2
5.2
5.1
5.1
Output Voltage (V)
Output Voltage (V)
At TA = 25ºC
5 4.9 4.8 4.7
5 4.9 4.8 4.7
4.6 -45
-5 35 75 115 Junction Temperature (qC)
4.6 -45
155
-5 35 75 115 Junction Temperature (qC)
D011
VI = 6 V
1200
11
1100
10
1000
9
900
Output Current (mA)
Output Voltage (V)
Figure 3. Output Voltage vs Junction Temperature
12
8 7 6 5 4 3
800 700 600 500 400 300
2
200
1
100
0 1
2
3 4 5 6 7 Input Voltage (V)
8
9
0 -45
10
-5 35 75 115 Junction Temperature (qC)
D013
Figure 4. Output Voltage vs Input Voltage
155 D002
Figure 5. Output Current vs Junction Temperature
3.5
12 11
Current Consumption (mA)
3 Iq – Current Consumption (mA)
D012
VI = 28 V
Figure 2. Output Voltage vs Junction Temperature
0
155
2.5 2 1.5 1 0.5
10 9 8 7 6 5 4 3 2 1
0 0
25
50
75
100
125
150
175
200
0 0
Output Current (mA)
VI = 13.5 V
50
100 150 200 250 300 350 400 Output Current (mA) D003
VI = 13.5 V
Figure 6. Current Consumption vs Output Current
Figure 7. Current Consumption vs Output Current
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Typical Characteristics (continued) 800
8
700
7
600
6
Charge Current (PA)
Dropout Voltage (mV)
At TA = 25ºC
500 400 300 200
0
100
200 300 400 Output Current (mA)
500
2
-5 35 75 115 Junction Temperature (qC)
D009
TJ = 25°C
VI = 13.5 V
Figure 8. Dropout Voltage (Vdo) vs Output Current
155 D001
VD = 1 V
Figure 9. Charge Current (ID,C) vs Junction Temperature 100
4 VDU VDRL
3.5
90 80
3
Ripple Rejection (dB)
Delay Switching Threshold (V)
3
0 -45
0
2.5 2 1.5 1
70 60 50 40 30 20
0.5 0 -45
10 -5 35 75 115 Junction Temperature (qC)
0 10 20 50 100
155 D009
VI = 13.5 V
VI = 13.5 V
Figure 10. Delay Switching Threshold vs Junction Temperature 100
100
90
90
80
80
70 60 50 40 30
50 40 30 20 10
VI = 13.5 V
Load = 200 mA
100000
0 10
100
D005
COUT = 22 µF
Figure 12. Power-Supply Ripple Rejection vs Frequency
D004
COUT = 22 µF
60
10 1000 10000 Frequency (Hz)
Load = 1 mA
100000
70
20
0 10 20 50 100
1000 10000 Frequency (Hz)
Figure 11. Power-Supply Ripple Rejection vs Frequency
Ripple Rejection (dB)
Ripple Rejection (dB)
4
1
100
8
5
VI = 13.5 V
1000 10000 Frequency (Hz)
Load = 400 mA
100000 D006
COUT = 22 µF
Figure 13. Power-Supply Ripple Rejection vs Frequency
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Typical Characteristics (continued) At TA = 25ºC 90
Junction-to-Ambient Thermal Resistance (qC/W) on 736 mm 2
80 Junction-to-Ambient Thermal Resistance (qC/W)
100 50
1-oz Copper 2-oz Copper
70 60 50 40 30
200
400 600 800 1000 1200 Copper Land-Pad Area (mm2)
1400
2 1 0.5
50% Duty Cycle 20% Duty Cycle 10% Duty Cycle 5% Duty Cycle 2% Duty Cycle 1% Duty Cycle 0.5% Duty Cycle 0.2% Duty Cycle Non-Normalized Response
0.2 0.1 0.05
0.02 0.01 1x10-6 1x10-5 1x10-4 1x10-3 1x10-2 1x10-1 1x100 1x101 1x102 1x103 Pulse-Width Time (s) D008
20 0
20 10 5
1600 D007
Figure 14. Thermal Resistance vs Copper Land Pad Area (JEDEC 51-3 Low-K Board)
Figure 15. Thermal Resistance vs Pulse Width Time for Various Duty Cycles
Stable Region
ESR (Ω)
ESR (Ω)
Unstable Region
Stable Region
Unstable Region
Load Capacitance (µF)
Load Capacitance (µF)
Figure 16. ESR Stability vs Load Current
Figure 17. ESR Stability vs Load Capacitance
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8 Parameter Measurement Information II
IN CI2 100 nF
CI1 1000 µF
1
5
IO
OUT
COUT 22 µF Rext 5 kΩ IRO
DELAY VI ID,d
ID,c
4
2
3
RESET
GND IGND
VD
VO
VRO
CD 47 nF
Figure 18. Test Circuit
10
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SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
9 Detailed Description 9.1 Overview The TLE4275-Q1 device is a monolithic integrated low-dropout voltage regulator offered in a 5-pin TO package. The device regulates an input voltage up to 45 V to VOUT = 5 V (typical). The device can drive loads up to 450 mA and is short circuit proof. At over temperature, the incorporated temperature protection turns off the TLE4275-Q1 device. The device generates a reset signal for an output voltage, VOUT,rt, of 4.65 V (typical). By the use of an external delay capacitor, one can program the reset delay time.
9.2 Functional Block Diagram
Temperature Sensor
Saturation Control and Protection Circuit
1
5
IN
OUT
Bandgap Reference
4
Reset Generator
DELAY
2
RESET
3 GND
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TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
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9.3 Feature Description 9.3.1 Regulated Output (OUT) The OUT terminal is the regulated 5-V output. The output has current limitation. During initial power up, the regulator has a soft start incorporated to control the initial current through the element. In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load current. 9.3.2 Power-On-Reset (RESET) The power-on-reset is an output with an external pull up resistor to the regulated supply. The reset output remains low until the regulated VO exceeds approximately 4.65 V and the power-on-reset delay has expired. 9.3.3 Reset Delay Timer (DELAY) An external capacitor on this terminal sets the timer delay before the reset terminal is asserted high. The constant output current charges an external capacitor until the voltage exceeds a threshold to trip an internal comparator. The reset pulse delay time td, is defined with the charge time of an external capacitor DELAY. Cdelay ´ VDU td = I D,c (1)
9.4 Device Functional Modes 9.4.1 Low-Voltage Tracking At low input voltages, the regulator drops out of regulation and the output voltage tracks input minus a voltage based on the load current (IO) and switch resistance (R(SW)). This allows for a smaller input capacitor and can possibly eliminate the need of using a boost convertor during cold-crank conditions.
12
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SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information Figure 19 shows typical application circuits for the TLE4275-Q1. Based on the end-application, different values of external components can be used. An application can require a larger output capacitor during fast load steps in order to prevent a reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response.
10.2 Typical Application TLE4275 Vbat
Vout OUT
IN C1
C3
RESET
DELAY
C2
R1
GND
Figure 19. Typical Application Diagram 10.2.1 Design Requirements For this design example, use the parameters listed in Table 1. Table 1. Design Parameters DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
4 to 40 V
Output voltage
5V
Output current rating
400 mA
Output capacitor range
10 to 500 µF
Output capacitor ESR range
1 mΩ to 20 Ω
DELAY capacitor range
100 pF to 500 nF
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13
TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
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10.2.2 Detailed Design Procedure To • • • • •
begin the design process, determine the following: Input voltage range Output voltage Output current rating Output capacitor Power-up reset delay time
10.2.2.1 Power-Up Reset Capacitance To calculate the power-up reset capacitance, use Equation 2. Cdelay ´ VDU td = I D,c
Cdelay t d =
t d ´ I D,c VDU
=
t d ´ 5.5 ´ 10-6 1.8
(2)
10.2.2.2 Thermal Consideration Calculate the power dissipated by the device according to Equation 3. PT = IO × (VI – VO) + VI × IQ
where • • • •
PT = Total power dissipation of the device. IO = output current VI = input voltage VO = output voltage
(3)
After determining the power dissipated by the device, calculate the junction temperature from the ambient temperature and the device thermal impedance. TJ = TA + RθJA × PT
(4)
10.2.3 Application Curves Load = 200 mA, Cin = 22 µF, Cout = 10 µF
CH1：Vout, CH2: Vin, CH3: Vreset. Figure 20. Power Up Waveform
14
CH1：Vout, CH2: Vin, CH3: Vreset. Figure 21. Power Down Waveform
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SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
11 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 4 V and 40 V. This input supply must be well regulated. If the input supply is located more than a few inches from the TLE4275-Q1 device, an electrolytic capacitor with a value of 47 µF and a ceramic by capacitor are recommended to add at the input.
12 Layout 12.1 Layout Guidelines •
•
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because of the negative impact on system performance. Vias and long traces can also cause instability. Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure stability. Every capacitor must be placed as close to the device as possible and on the same side of the PCB as the regulator.
12.2 Layout Example 180
RESET
NC
NC
IN
DELAY
NC
OUT
NC
NC
NC
NC
NC
NC
NC
GND
NC
Connect through bottom layer
Vin
Power Ground
Output filter capacitor, place close to chip Vout
Input by capacitor
Power Ground
NC
NC
NC
NC
Figure 22. TLE4275-Q1 HTSSOP Layout Design Example
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TLE4275-Q1 SLVS647I – AUGUST 2006 – REVISED NOVEMBER 2014
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13 Device and Documentation 13.1 Documentation 13.1.1 Related Documentation For related documentation see the following: TLE4275-Q1 Low Temperature Stability, SLVA501
13.2 Trademarks All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains , acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2014
PACKAGING INFORMATION Orderable Device
Status (1)
Package Type Package Pins Package Drawing Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking (4/5)
TLE4275QKTTRQ1
ACTIVE
DDPAK/ TO-263
KTT
5
500
Green (RoHS & no Sb/Br)
CU SN
Level-3-245C-168 HR
-40 to 125
TLE4275Q
TLE4275QKVURQ1
ACTIVE
TO-252
KVU
5
2500
Green (RoHS & no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
TLE4275Q
TLE4275QPWPRQ1
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS & no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLE4275Q
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com
4-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLE4275QKTTRQ1
Package Package Pins Type Drawing
SPQ
DDPAK/ TO-263
5
500
330.0
24.4
KTT
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm)
B0 (mm)
K0 (mm)
P1 (mm)
W Pin1 (mm) Quadrant
10.6
15.8
4.9
16.0
24.0
Q2
TLE4275QKVURQ1
TO-252
KVU
5
2500
330.0
16.4
6.9
10.5
2.7
8.0
16.0
Q2
TLE4275QPWPRQ1
HTSSOP
PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com
4-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLE4275QKTTRQ1
DDPAK/TO-263
KTT
5
500
340.0
340.0
38.0
TLE4275QKVURQ1
TO-252
KVU
5
2500
340.0
340.0
38.0
TLE4275QPWPRQ1
HTSSOP
PWP
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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